The present invention relates in general to programmable logic devices (PLDs), and in particular to a PLD that can be dynamically partially reconfigured without disturbing previous configuration.
Programmable logic devices are digital, user-configurable integrated circuits that can implement complex custom logic functions. For the purposes of this description, the term PLD encompasses all digital logic circuits configured by the end user, including programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), erasable and complex PLDs and the like. Such devices are sometimes referred to as, for example, PALs, FPLAs, EPLDs, EEPLDs, LCA, and CPLDs. The basic building block of a PLD is a logic element, sometimes referred to as a macro cell. Typically, a logic element contains combinatorial logic as well as a programmable flipflop to implement sequential logic.
One approach to implementing a logic element utilizes a programmable memory structure that includes memory cells for storing information corresponding to a desired logic configuration. The memory structure is then connected to a look-up table that, based on a logical combination of its several inputs, produces a selected bit from the memory structure at an output. To be able to perform sequential logic, the output of the look-up table also feeds an input of a configurable register.
The programming element in such a logic element can be implemented in a variety of technologies: fusible links, mask or electrically programmable read-only memory cells, or static random access memory (SRAM) cells. The complexity of the required programming circuitry varies with the type of memory technology used. For example, in the case of a PLD that uses SRAM technology as the logic configuration host, address decoding logic is required to load the programming data into the memory cells.
To program the PLDs, configuration data is usually loaded into the device upon power up. Existing PLDs commonly provide for a large shift register that is loaded with configuration data upon power up. The configuration data is then shifted into its destination configuration bits in a first-in first-out (FIFO) fashion. For example, to program a block or sub-group of SRAM based logic elements in a PLD, there may be multiple address lines provided to access various bits, but only one data line that travels through a string of SRAM cells. Thus, data must travel through the entire array of SRAM bits to fully program the PLD.
In most applications, before entering the user mode, the PLD is generally required to go through only one full cycle of programming. Configuration data is therefore loaded into the PLD once and there is usually no need to subsequently change the state of randomly located configuration bits. The FIFO approach in programming the SRAM based PLD thus works efficiently for most applications. This approach, however, suffers from drawbacks in those applications that require partial reconfiguration. Because data must travel through the entire array, for all practical purposes, FIFO programming does not allow the PLD to be partially reconfigured. That is, to reconfigure or change the state of one or several configuration bits in the middle of the SRAM array, the entire array must be reconfigured. This type of reconfiguration stops the programmed logic flow as well and thus cannot be performed without disturbing the PLD logic functionality.
A fast growing field of application for PLDs has been emulation and prototyping systems. Emulation systems help in debugging complex designs with quick turn-around which ensure successful time-to-market for the final product. PLDs are particularly suited for such debug systems since they provide the flexibility required by design adjustments resulting from design errors or enhancements. Often, the emulation system manufacturers are interested not only in the proper system design, but also in the near proper operation of the system when one or a small number of faults are present in the design. In testing for proper system operation, a useful feature for production quality testing is the ability to insert a fault. Test vectors are then run to see if the fault is detected. Failure to detect the fault indicates that the test program needs further refinements. Other systems are required to be fault tolerant. For these systems, it is desirable to insert a fault and observe that the system takes the designed fault recovery steps and continues to operate.
In both of the above cases, it is highly desirable to be able to change only a small part of the design while retaining the bulk of the configuration intact. For example, fault grading a set of production test vectors requires a large number of system reconfigurations in order to inject faults. Such a fault grading of a system using conventional PLDs where the entire PLD would have to be reconfigured each time, would be prohibitively time consuming.
A further requirement of testing fault tolerant systems is "crisp" fault injection while the system is still running at full speed. Crisp fault injection refers to changing the state of a configuration bit all at once without intermediate configurations being altered between the initial and destination configurations. Only when the fault can be crisply introduced into a running system can the complete fault recovery behavior be observed dynamically (i.e., on-the-fly).
From the foregoing it can be appreciated that the conventional FIFO approach to PLD configuration fails to adequately meet the requirements of many new applications. It is therefore desirable to provide a PLD programming technique that allows for static or dynamic partial reconfigurability without disturbing design functionality.